The present invention relates to a semiconductor device, for example, a dynamic random access memory (DRAM) process for a semiconductor device.
In a DRAM process for a logic circuit region and a DRAM cell region, an interlayer insulating film between a diffusion layer (Diffusion) and a first metal wiring layer (M1 wire) has a large thickness, increasing the height of a contact (CT) coupling the diffusion layer to the first metal wiring layer. This increases the resistance and parasitic capacitance of the contact, leading to a delay of a logic circuit region and large power consumption.
For wiring in the logic circuit region and contacts, a DRAM bit line (DBL wire) including a DRAM cell circuit between the diffusion layer and the first metal wiring layer in the DRAM cell region is proposed and a DRAM bit contact (DBLCT) coupling a DBL wiring layer to the diffusion layer is also proposed, reducing the resistance and parasitic capacitance of the contact and the delay of a logic section (Japanese Unexamined Patent Publication No. 2008-251763).
A gate coupled to a DBLCT is subjected to plasma damage by plasma charge generated in the formation of the DBLCT. Plasma damage is a failure caused by increased charge in the plasma process of thin-film device fabrication. The increased charge causes a high electric field on the gate oxide film of a transistor so as to apply a tunnel current, resulting in a break or deterioration of the gate oxide film. This directly leads to faulty transistors and a reduction in manufacturing yield.
In the case of dense DBLCTs in a DRAM cell region, however, plasma charge is dispersed to peripheral wires and DBLCTs, thereby preventing plasma damage.
Generally known plasma damage protecting elements may be peripheral wires or contacts (K Miyamoto et al., “Impact of Pattern Density on Plasma Damage of CMOS LSIs,” 1996 IEEE, pp. IEDM 96-739-IEDM 96-742). Furthermore, known dummy elements for plasma damage may be contacts having no wires coupled to the tops of the contacts (Japanese Unexamined Patent Publication No. 2006-344773). Moreover, the formation of dummy contact pads in separation grooves is proposed to reduce etching residue around the separation grooves during dry etching (Japanese Unexamined Patent Publication No. 2008-016705).
Typically, the use of DBLCTs in a logic circuit region requires the insertion of plasma damage protecting elements because the contact density of the logic circuit region is lower than that of a DRAM cell region.
In the logic circuit region, however, equal gate dimensions make it difficult to dispose dummy bit contacts around an active diffusion layer including a transistor. Moreover, the placement of the dummy bit contacts increases a gate pitch, leading to a larger chip size. Dummy gates for plasma damage cannot be added to gates coupled to DBLCTs because the dummy gates affect delay performance and a chip area.
Although dummy elements for plasma damage have been conventionally known, methods for efficiently disposing the dummy elements without affecting a chip area and delay performance are not available.